Browsing by Author "Yankey, Jephthah"

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    A 40–100 MHz phase-locked loop frequency synthesizer with built-in self-test
    (2012) Yankey, Jephthah
    The Phase locked loop (PLL) is one of the most important devices in modern electronic systems. PLLs are widely used for clock generation or frequency synthesis in communication systems, computers, radio and other electronic applications. However, due to the use of expensive external equipment and amount of time involved, traditional VLSI testing methods are inefficient for testing of PLLs. In this thesis, a fully functional PLL frequency synthesizer which operates from 40MHz to 100MHz is designed. The designed PLL exhibits phase noise of -71dBc/Hz at 1kHz, which is low enough for a wide array of applications. To solve the testing problem, Built-In Self-Test (BIST) is employed. A BIST scheme based on a defect-oriented method of testing is proposed. A prototype adds BIST circuitry, a good part of which is derived from existing components of the original design. The PLL BIST scheme is generic and hence portable to similar PLL designs. One significant addition unit is a simple response collector that combines shifting and counting functionalities. The entire system is designed in a typical CMOS process using a 3V power supply which is commonly found in today’s portable products. Spectre® simulations of the PLL show that it is capable of synthesizing any frequency between 40 and 100MHz within a reasonably short acquisition time. The output waveform of the generated signal is clean and shows no spikes whatsoever. Experimental simulations also reveal that the BIST circuitry is capable of generating the exact test pattern needed. It also performs efficiently all the unique checks which make up the PLL BIST. The final test output is very consistent and produces the same results for a number of different runs of the simulation.
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    Design of a fully integrated VHF CP-PLL frequency synthesizer with an all-digital defect-oriented built-in self-test
    (The Journal of Engineering, 2022-10-28) Kommey, Benjamin; Boateng, Kwame Osei; Yankey, Jephthah; Addo, Ernest Ofosu; Agbemenu, Andrew Selasi; Tchao, Eric Tutu; Akowuah, Bright Yeboah
    This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of −132 dBc/Hz at 1 MHz and consumes 1.8mWon a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ complementary metal-oxide-semiconductor process.